The present invention relates to a semiconductor memory device, particularly to a sensing device which senses a voltage on a bit line with an input/output line.
In a dynamic random access memory (DRAM), information of a memory cell is presented on a bit line in the form of voltage by a sense amplifier, and this voltage is sent to an input/output line by column decoding. A voltage difference between a bit line pair corresponding to a bit information is sufficiently amplified by the sense amplifier. When data read from a memory cell is sent to an input/output line, charge sharing occurs twice. First, when charge saved in the memory cell flows into the bit line because of word line driving, and second, when charge in the bit line is loaded on the input/output line.
Referring to a column circuit of a dynamic RAM in FIG. 1, a bit line equivalent signal .phi.EQ is disabled in "low" state and a word line WL1 is operated, and thereafter charge in a memory cell MC1 is sent to the bit line BL. At this time, a reference potential of a given level by a dummy cell is presented on the bit line BL. When n-type sense amplifier 12 comprised of NMOS transistors cross-coupled between the bit line pair BL, BL is enabled by a sensing clock LAG of "high" state, voltage difference between the bit line pair BL, BL is amplified. When the voltage difference between the bit line pair BL, BL is sufficiently amplified, a column selection signal CSL is enabled in "high" state, to thereby connect the bit line pair to input/output line pair. Signals and clocks, however, used in this sensing and sending process, are generated inside the semiconductor memory device.
FIG. 2A shows a conventional circuit for generating the sensing clock LAG. Referring to the conventional sensing clock generating circuit shown in FIG. 2A and a conventional sensing timing diagram shown in FIG. 2C, when the strobe clock .phi.S according to an enabled row address strobe signal RAS is enabled in "high" state, a PMOS transistor is turned on and the sensing clock LAG is enabled in "high" state. Then, as shown in FIG. 1, a pull down NMOS transistor 13 in a n-type sense amplifier 12 is turned on and current I.sub.s flows into a ground voltage terminal Vss from a discharging node 14, so that the n-type sense amplifier 12 is driven. When the voltage difference between the bit line pair is sufficiently high, as shown in FIG. 2B, the column selection signal CSL corresponding to a signal output from a column pre-decoder (not shown) and a column gate signal .phi.YE, is enabled in "high" state, to thereby connect the bit line pair to an input/output line pair IO/IO. In this case, like a dotted circle shown in FIG. 2C, charge sharing of the input/output line and the bit line causes the voltage difference between the bit line pair to be reduced to .DELTA.VBL. The input/output line, conventionally known, is precharged and equalized to V.sub.cc -V.sub.th. When the bit line and the input/output line are connected, charge sharing is inevitable. So heavily reduced voltage difference between the bit line pair as described above causes data access time on the input/output line to be delayed. Therefore, there are occasions when a high density and high speed dynamic RAM cannot achieve desired speed operation because of delayed sensing time.